The invention lies in the field of integrated circuits. The invention relates to a method for operating a memory cell configuration having dynamic gain memory cells.
At present, a so-called one-transistor memory cell is usually used as a memory cell of a memory cell configuration. Such a memory cell includes a transistor and a capacitor on which information is stored in the form of a charge. By driving the transistor through a word line, it is possible for the charge on the capacitor to be read out through a bit line. Because the charge of the capacitor drives the bit line and a signal generated by the charge is intended to remain identifiable despite background noise, the capacitor must have a minimum capacitance. The minimum capacitance requirement placed on the capacitor constitutes an obstacle to increasing the packing density of the memory cell configuration because the size of the capacitor cannot be arbitrarily reduced.
The problem is avoided in an alternative memory cell configuration in which so-called gain cells, i.e., dynamic gain memory cells, are used as memory cells. In such a configuration, too, the information is stored in the form of an electrical charge. However, the electrical charge does not have to directly drive a bit line. Rather, it is stored on a gate electrode of a memory transistor and serves only for controlling the latter, for which purpose a very small quantity of electrical charge is already sufficient.
European Patent Application 537203, corresponding to U.S. Pat. No. 5,327,374 to Krautschneider et al., describes a memory cell configuration in which a memory cell is a dynamic gain memory cell including a selection transistor, a memory transistor, and a Shottky junction. A gate electrode of the selection transistor is connected to a word line. The selection transistor and the memory transistor are connected in series and between a bit line and a voltage terminal at which an operating voltage is present. The Shottky junction is connected between the gate electrode of the memory transistor and a source/drain region of the selection transistor. To write information to a memory cell, the associated word line drives the associated selection transistor. Depending on the type of information, a low voltage UBL or a high voltage UBH is applied to the bit line. The charge on the gate electrode of the memory transistor that is established in the process is dependent on the voltage on the bit line and represents the information. To read out the information, the selection transistor is driven through the word line and the low voltage UBL is applied to the bit line. If the gate electrode of the memory transistor was previously charged by the high voltage UBH on the bit line, then a voltage difference between the gate electrode and a source/drain region of the memory transistor arises that is greater than a threshold voltage of the memory transistor, with the result that a signal charge is brought about by a current between the voltage terminal and the bit line. If the gate electrode of the memory transistor was charged by the low voltage UBL on the bit line, then no voltage difference between the gate electrode and the source/drain region of the memory transistor arises that is greater than the threshold voltage of the memory transistor, resulting in no current flow.
The article by M. Heshami et al., xe2x80x9cA 250-MHz Skewed-Clock Pipelined Data Buffer,xe2x80x9d IEEE Journal of Solid-State Circuits, Vol. 31, No. 3 (1996) 376, describes a memory cell configuration in which a memory cell is a dynamic gain memory cell that includes a first selection transistor, a memory transistor, and a second selection transistor. The first selection transistor is connected between a first bit line and a gate electrode of the memory transistor. A gate electrode of the first selection transistor is connected to a first word line. The second selection transistor is connected between a source/drain region of the memory transistor and a second bit line. A gate electrode of the second selection transistor is connected to a second word line. A further source/drain region of the memory transistor is connected to a voltage terminal. To write an information item to the gate electrode of the memory transistor, the first selection transistor is driven through the first word line, resulting in the establishment, on the gate electrode of the memory transistor, of a voltage that is dependent on a voltage on the first bit line, the magnitude of which, in turn, depends on the information to be written. To read out the information, the second selection transistor is driven through the second word line. Depending on the information, i.e., depending on the voltage on the gate electrode of the memory transistor, the memory transistor is in the on state or in the off state, and a current does or does not flow between the voltage terminal and the second bit line.
It is accordingly an object of the invention to provide a method for operating a memory cell configuration having dynamic gain memory cells that overcomes the hereinafore-mentioned disadvantages of the heretofore-known devices and methods of this general type and, in which, for a given operating voltage, a signal charge is greater than in comparison with the prior art.
With the foregoing and other objects in view, there is provided, in accordance with the invention, a method for operating a memory cell configuration having dynamic gain memory cells including the steps of providing memory cells each having at least one memory transistor with a gate electrode and first and second drain/source regions, writing a first information item to a memory cell by charging a gate electrode of a memory transistor of the memory cell with a first voltage, writing a second information item to the memory cell by charging the gate electrode of the memory transistor with a second voltage, respectively reading out the first information item and the second information item by applying an operating voltage to a first source/drain region of the memory transistor and applying a read-out voltage to a second source/drain region of the memory transistor, setting the first voltage to lie between the second voltage and the readout voltage, setting the read-out voltage to lie between the first voltage minus a threshold voltage of the memory transistor and the second voltage minus the threshold voltage of the memory transistor, and selecting the operating voltage such that the memory transistor is in an off state when the first information item is read out.
Providing a signal charge is greater than in comparison with the prior art can be achieved with a method for operating a memory cell configuration having dynamic gain memory cells, in which the memory cells each include at least one memory transistor. To write a first information item to one of the memory cells, a gate electrode of the associated memory transistor is charged such that a first voltage is present on it. To write a second information item to the memory cell, the gate electrode of the memory transistor is charged such that a second voltage is present on it. In each case, in order to read out the first information item and to read out the second information item, an operating voltage is applied to a first source/drain region of the memory transistor, and a read-out voltage is applied to a second source/drain region of the memory transistor. The first voltage lies between the second voltage and the read-out voltage. The read-out voltage lies between the first voltage minus a threshold voltage of the memory transistor and the second voltage minus the threshold voltage of the memory transistor.
The dynamic gain memory cell includes the memory transistor, on whose gate electrode the information is stored in the form of a charge. During writing, the charge is set such that, in the case of the first information item, the memory transistor is in the off state, i.e., no current can flow through the memory transistor, whereas it is in the on state in the case of the second information item. In contrast to the read-out of the first information item, a signal charge flows through the memory transistor when the second information item is read out. The signal charge flows between the first source/drain region and the second source/drain region of the memory transistor. A voltage difference between the gate electrode of the memory transistor and the second source/drain region of the memory transistor is greater than if the read-out voltage were equal to the first voltage because the read-out voltage is not equal to the first voltage and does not lie between the first voltage and the second voltage. An electrical resistance of the memory transistor is, thus, smaller, resulting in a particularly large signal charge flow therethrough. In comparison with the prior art, in which the first voltage is equal to the read-out voltage, a larger signal charge can flow for the same operating voltage. In comparison with the prior art, in which the first voltage is equal to the read-out voltage, the same signal charge can flow for a smaller operating voltage. Formulated in general terms, the operating voltage divided by the signal charge is smaller than in comparison with the prior art. For a given operating voltage, a signal charge is greater than in comparison with the prior art. The read-out voltage lies between the first voltage minus the threshold voltage of the memory transistor and the second voltage minus the threshold voltage of the memory transistor, so that the memory transistor is in the off state when the first information item is read out, and is in the on state when the second information item is read out. The process is based on the fact that a transistor is in the on state when a voltage difference between its gate electrode and at least one source/drain region is greater than the absolute value of its threshold voltage. The operating voltage is chosen such that the memory transistor is in the off state when the first voltage is present at its gate electrode. Otherwise, the memory transistor would be in the on state independently of the magnitude of the read-out voltage.
For example, if the memory transistor is an n-channel transistor in which the first and second source/drain regions are n-doped, then the second voltage is greater than the first voltage and the first voltage is greater than the read-out voltage. The read-out voltage is greater than the first voltage minus the threshold voltage of the memory transistor and less than the second voltage minus the threshold voltage of the memory transistor. The threshold voltage is greater than the first voltage minus the operating voltage. The threshold voltage is preferably greater than the second voltage minus the operating voltage. In such a case, the operating voltage may be present at the first source/drain region of the memory transistor even when the read-out voltage is not present at the second source/drain region of the memory transistor, without the memory transistor, therefore, being in the on state.
The same applies analogously to a memory cell configuration in which the memory transistor is a p-channel transistor. Thus, the first source/drain region and the second source/drain region of the memory transistor are p-doped. It is necessary merely to change the signs of the voltages. For example, the second voltage is, thus, less than the first voltage, and the first voltage is less than the read-out voltage.
Hereinafter, xe2x80x9cvoltage x is almost equal to yxe2x80x9d means that x is as close as possible to y such that a given condition is still fulfilled.
The read-out voltage is preferably almost equal to the first voltage minus the threshold voltage of the memory transistor, i.e., is actually still large enough that, during read-out, no current flows through the memory transistor when the first voltage is present at its gate electrode. Thus, the sum of the read-out voltage and the threshold voltage is approximately 0 volts. Under the condition that the memory transistor is in the off state when the first information item is read out, the voltage difference between the second voltage and the read-out voltage is maximal in this case, resulting the memory transistor conducting a maximal amount of current. The signal charge is particularly large.
The first voltage is 0 V, for example. In such a case, the read-out voltage preferably amounts to almost the negative threshold voltage of the memory transistor. For the case where the memory transistor is an n-channel transistor, the read-out voltage is somewhat greater than the negative threshold voltage. If the threshold voltage is 1 volt, for example, then the read-out voltage is, e.g., minus 0.8 volts.
In accordance with another mode of the invention, the memory cell may include at least one selection transistor whose first source/drain region is connected to a bit line, whose second source/drain region is connected to the gate electrode of the memory transistor, and whose gate electrode is connected to a word line. To write the first information item, the word line is driven such that the gate electrode of the memory transistor is electrically connected to the bit line. A first bit line voltage is applied to the bit line such that the first voltage is present at the gate electrode of the memory transistor. To write the second information item to the memory cell, the word line is driven such that the gate electrode of the memory transistor is electrically connected to the bit line. A second bit line voltage is applied to the bit line such that the second voltage is present at the gate electrode of the memory transistor.
In accordance with a further mode of the invention, the second bit line voltage may be equal to the operating voltage.
For the sake of simplicity, reference is made below to a memory transistor that is an n-channel transistor. However, the same applies analogously to the case where the memory transistor is a p-channel transistor. It is necessary merely to change the signs of the voltages.
The selection transistor is preferably likewise an n-channel transistor if the memory transistor is an n-channel transistor.
In accordance with an added mode of the invention, in a first case, during the writing of the second information item, the word line can be driven by having applied to it a voltage that is equal to the sum of the operating voltage and a threshold voltage of the selection transistor. The selection transistor remains in the on state for as long as a voltage difference between its gate electrode and the first source/drain region or the second source/drain region is greater than its threshold voltage. Because the sum of the operating voltage and the threshold voltage is present at the gate electrode of the selection transistor and the operating voltage is present on the bit line, a current can flow until the operating voltage is likewise present at the gate electrode of the memory transistor. Consequently, the second voltage is equal to the operating voltage in the first case.
In accordance with an additional mode of the invention, in a second case, during the writing of the second information item, the operating voltage applied to the word line drives the word line. In such a case, during the writing of the second information item, current flows through the selection transistor only until the operating voltage minus the threshold voltage of the selection transistor is present at the gate electrode of the memory transistor. The charge on the gate electrode of the memory transistor is lower than in the first case. Because, during the read-out of the second information item, the voltage difference between the gate electrode and the second source/drain region of the memory transistor is smaller than in the first case, less current flows through the memory transistor than in the first case. The signal charge is thus smaller.
To simplify the method, it is advantageous to apply the same voltage to the word line during the writing of the first information item as during the writing of the second information item. In the second case, during the writing of the first information item, a voltage difference between the gate electrode of the selection transistor and its first source/drain region is then smaller than in the first case. As a result, the gate dielectric of the selection transistor can be thinner. The small thickness of the gate dielectric is advantageous because it leads to a high transconductance and to a high performance of the selection transistor. Due to the small thickness of the gate dielectric, performance characteristic data of the selection transistor can be so good that they satisfy the requirements for transistor of a logic circuit. Consequently, both the transistors of the memory cell configuration and the transistors of the logic circuit can be produced simultaneously on one chip.
The value of the voltage on the word line can be adapted to the respective requirements. The larger the signal charge is intended to be, the higher the voltage chosen. Preferably, the voltage is not greater than in the first case described above, because the second voltage at the gate electrode of the memory transistor cannot exceed the second bit line voltage. The thinner the gate dielectric is intended to be, the smaller the voltage chosen. It lies within the scope of the invention to make a compromise, so that the voltage on the word line lies between the operating voltage and the sum of the operating voltage and the threshold voltage.
To reduce the process complexity during the fabrication of the memory cell configuration, it is advantageous if the selection transistor and the memory transistor are produced simultaneously, so that their gate dielectrics have the same thicknesses. The selection transistor and the memory transistor can have the same threshold voltage.
In accordance with yet another mode of the invention, the memory cell may include at least one diode connected between the second source/drain region of the selection transistor and the gate electrode of the memory transistor such that it becomes more difficult for charge to flow away from the gate electrode of the memory transistor to the second source/drain region of the selection transistor. Thus, the reverse direction of the diode points from the gate electrode of the memory transistor to the second source/drain region of the selection transistor. The second source/drain region of the selection transistor is connected to the second source/drain region of the memory transistor. To read out the first information item and to read out the second information item, the word line is driven, so that the selection transistor acts as a read-out transistor. Thus, only one bit line and one word line are provided per memory cell. When choosing the thickness of the gate dielectric of the selection transistor, it is necessary to take into account not only the difference between the voltage on the word line and the first bit line voltage but also the difference between the voltage on the word line and the read-out voltage.
Hereinafter, the term xe2x80x9cread-out transistorxe2x80x9d is interchangeable with the term xe2x80x9cselection transistorxe2x80x9d for the case of a memory cell with diode.
The memory cell configuration can be constructed particularly simply if the same voltage is applied to the word line both during writing and during read-out.
In the first case described above, the maximum voltage difference between the gate electrode and the first source/drain region of the selection transistor is then equal to the sum of the operating voltage and the threshold voltage minus the read-out voltage. The voltage difference is, therefore, almost equal to the sum of the operating voltage and twice the threshold voltage. In the second case described above, the maximum voltage difference between the gate electrode and the first source/drain region of the selection transistor is equal to the operating voltage minus the read-out voltage. Thus, the voltage difference is almost equal to the sum of the operating voltage and the threshold voltage of the memory transistor.
In accordance with yet a further mode of the invention, the memory cell may be a three-transistor memory cell, as is described, e.g., in M. Heshami et al. (see above). For example, the memory cell includes a read-out transistor whose first source/drain region is connected to the second source/drain region of the memory transistor. To read out the first information item and to read out the second information item, a gate electrode of the read-out transistor is driven. The gate electrode of the read-out transistor is connected to a further word line, for example. A second source/drain region of the read-out transistor may be connected to a further bit line through which the signal charge is determined. The word line and the further word line may be identical. In such a case, the bit line and the further bit line are different from one another. The bit line and the further bit line may be identical. In such a case, the word line and the further word line are different from one another.
If the memory cell includes the diode, the gate dielectric of the selection transistor can be particularly thin if a smaller voltage is applied to the word line during read-out than during writing. Preferably, the voltage on the word line is adapted to the read-out voltage such that a voltage drop across the gate dielectric of the selection transistor is the same both during writing and during read-out. In the first case described above, the voltage on the word line during read-out is then equal to the sum of the operating voltage, the threshold voltage, and the read-out voltage. As a result, the maximum voltage difference between the gate electrode and the first source/drain region of the selection transistor that is dropped across the gate dielectric of the selection transistor during operation of the memory cell configuration is equal to the sum of the operating voltage and the threshold voltage. The voltage on the word line during read-out is, e.g., almost equal to the operating voltage. In the second case described above, the voltage on the word line during read-out is then equal to the sum of the operating voltage and the read-out voltage. As a result, the maximum voltage difference between the gate electrode and the first source/drain region of the selection transistor that is dropped across the gate dielectric of the selection transistor during operation of the memory cell configuration is equal to the operating voltage. The voltage on the word line during read-out is, e.g., almost equal to the operating voltage minus the threshold voltage of the read-out transistor.
To ensure that an increased leakage current is not produced between the first source/drain region of the read-out transistor and a substrate in which the first source/drain region of the read-out transistor is disposed, when the read-out voltage is present, it is advantageous if a voltage that is not greater than the read-out voltage is present across the substrate. P-n junctions between source/drain regions of the transistors and the substrate are then reverse-biased.
The first source/drain region of the memory transistor may be connected to a voltage terminal that is kept constant at the operating voltage.
In accordance with a concomitant mode of the invention, the memory cell configuration of the memory cells is in a substrate across which there is a voltage equal to or less than the read-out voltage when the read-out transistor is an n-channel transistor, and equal to or greater than the readout voltage when the read-out transistor is a p-channel transistor.
Other features that are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a method for operating a memory cell configuration having dynamic gain memory cells, it is, nevertheless, not intended to be limited to the details shown because various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof, will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.